Technology thesis · Semiconductors & Chips
high conviction growthAdvanced Semiconductor Packaging
Advanced packaging – not transistor scaling – is now the primary bottleneck in AI chip production; TSMC's CoWoS capacity limits total GPU output globally.
Position maintained continuously · last reviewed Jun 3, 2026
The thesis
Core thesis
CoWoS (Chip-on-Wafer-on-Substrate) packaging bonds HBM memory dies onto GPU substrates. TSMC controls the great majority of leading-edge advanced packaging for AI chips. CoWoS capacity – not chip design, not HBM supply, but packaging – is what paces NVIDIA GPU output; it has been the limiting step on accelerator supply through 2023–2025, with the supply-demand gap only narrowing toward ~10% across 2026. Chiplet architectures (heterogeneous integration) are the future, making packaging the new Moore’s Law.
State of the art (2026)
State of the art (2026). Advanced packaging, not transistor scaling, is the bottleneck on AI-accelerator output: TSMC's CoWoS capacity limits how many GPUs and custom XPUs the industry can ship, and TSMC has been expanding it sharply year over year while CoWoS-L (large-reticle) and SoIC (3D stacking) push interposer size and stack height. The next high-value packaging workload is optical: TSMC's COUPE process co-packages silicon photonics with the switch or accelerator, and Nvidia, Broadcom and Ayar Labs are all building on it (brief 973). The scarce tier of the AI hardware stack is the leading-edge integration process, and it sits with the foundry.
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Signal stack
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Landscape map
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Catalyst calendar
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Technology roadmap
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Thesis changelog
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Change our mind
3 disconfirming conditions
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