Advanced Semiconductor Fabrication

State of the art (2026)

The 2nm era is live and TSMC owns it. N2 (GAA nanosheet) entered volume production in late 2025 and is ramping through 2026 with Apple's A20 as lead customer; TSMC's leading-edge fabs are reportedly sold out for the year. Samsung's SF2 has climbed to roughly 55-60% yield and won a $16.5bn Tesla AI5/AI6 deal, but still trails. Intel reached 18A high-volume manufacturing at Arizona Fab 52 (Panther Lake), though yields remain below profitable. On lithography, Intel leads High-NA EUV adoption while TSMC plans to skip it for A16/A14, sticking with 0.33-NA tools. Geographic diversification lags: Samsung's Taylor, Texas customer ramp has slipped to 2027.

The TSMC monopoly — why advanced fabrication is a one-player game

Below 5nm, semiconductor fabrication is not a competitive market — it is a natural monopoly disguised by the existence of nominal competitors. TSMC holds 90%+ of leading-edge external foundry revenue not because it has better chip architects, but because it has accumulated 30+ years of yield optimization that no competitor can replicate through capital expenditure alone. Samsung's 3nm Gate-All-Around process exists on paper but produces significantly lower yields than TSMC's N3E FinFET, meaning Samsung customers pay more per working die. Intel's foundry ambitions under Pat Gelsinger generated headlines but not competitive silicon — the 18A node has been delayed repeatedly, and Intel's credibility on timeline commitments is exhausted among the customer base that matters. The core insight sophisticated observers miss: fabrication IP is not in the transistor design (FinFET, GAA, CFET are known architectures), it is in the manufacturing process recipe — thousands of individual deposition, etch, lithography, and metrology steps, each calibrated through decades of empirical learning. The same design taped out at TSMC and at Samsung will produce different yield curves because the process knowledge is the actual intellectual property.

The China ceiling — EUV denial as permanent architecture constraint

SMIC demonstrated 7nm-class production in 2022 using multi-patterning DUV lithography — a genuine engineering achievement that required running certain layers through the lithography tool four or more times instead of once. But this approach hits a hard physical wall. At 5nm and below, multi-patterning DUV becomes economically unviable: yields crater, cycle times multiply, and defect rates compound with each additional pass. EUV lithography from ASML is the enabling technology for sub-5nm production, and export controls backed by the Netherlands, Japan, and the United States create a durable denial regime. China is investing heavily in domestic EUV development, but building an EUV scanner is arguably the most complex engineering challenge on earth — 100,000+ components, 13.5nm wavelength light generated by hitting tin droplets with a CO2 laser 50,000 times per second, mirrors polished to sub-atomic smoothness. ASML spent 20+ years and billions of euros getting here. China's domestic EUV efforts are credible in ambition but realistically a decade or more from production-grade capability. This means Chinese fabs face a permanent ceiling on process node capability for the foreseeable future, limiting China's ability to manufacture the most advanced AI and mobile processors domestically.

The geopolitics thesis — Taiwan as the most dangerous single point of failure

TSMC's fabs in Taiwan represent the single most consequential concentration of industrial capability in the global economy. Over 90% of the world's most advanced semiconductors are manufactured on an island 100 miles from a hostile superpower that claims sovereignty over it. No other supply chain risk in any industry approaches this magnitude. The TSMC Arizona fab (Fab 21) is the most visible attempt at geographic diversification, but it does not solve the problem — Phase 1 targets 4nm (a trailing-edge node by the time it reaches full production), staffing challenges have required flying in thousands of Taiwanese engineers, and the cultural friction between TSMC's intense Taiwanese work culture and American labor expectations has been widely documented. Japan's TSMC Kumamoto fab (JASM) and the planned European fab in Dresden serve mature nodes, not leading edge. RAPIDUS in Japan, backed by government subsidies and IBM's 2nm process IP, is the most ambitious non-TSMC greenfield attempt but faces the same yield-gap problem every new entrant confronts. The uncomfortable strategic reality: advanced fabrication cannot be meaningfully geographically diversified on a 5-year horizon. The process knowledge lives in TSMC's engineering corps in Hsinchu, and that knowledge does not transfer by building a building. The Arizona fab is an insurance policy, not a solution — and the premium is tens of billions of dollars for partial coverage.